A High-Level Synthesis Approach for a RISC-V RV32I-Based System on Chip and Its FPGA Implementation

A High-Level Synthesis Approach for a RISC-V RV32I-Based System on Chip and Its FPGA Implementation

Blog Article

In this paper, we present a RISC-V RV32I-based system-on-chip (SoC) design approach using the Vivado high-level synthesis (HLS) tool.The proposed approach consists of three separate levels: The first one is an HLS design and simulation purely in C++.The second one is a Verilog simulation of the HLS-generated Verilog implementation of the CPU core, a RAM unit initialized with a short assembly code, and a simple Teaspoon output port which simply forwards the output data to the simulation console.Finally, the third level is the implementation and testing of this SoC on a low-cost FPGA board (Basys3) running at a clock speed of 100 MHz.

A sample C code was compiled using the GNU RISC-V compiler tool chain and tested on the HLS-generated RISC-V RV32I core as well.The HLS design consists of a single C++ file with fewer than 300 lines, a single header file, and a testbench in C++.Our design objectives are that (1) the C++ code should be easy to read for an average engineer, and (2) the coding Gas Safety Valve style should dictate minimal area, i.e.

, minimal resource utilization, without significantly degrading the code readability.The proposed system was implemented for two different I/O bus alternatives: (1) a traditional single clock cycle delay memory interface and (2) the industry-standard AXI bus.We present timing closure, resource utilization, and power consumption estimates.Furthermore, by using the open-source synthesis tool yosys, we generated a CMOS gate-level design and provide gate count details.

All design, simulation, and constraint files are publicly available in a GitHub repo.We also present a simple dual-core SoC design, but detailed multi-core designs and other advanced futures are planned for future research.